The computer-aided design of an integrated circuit typically involves interconnecting various building blocks, commonly referred to as cells, which perform specified circuit functions. Such cells may correspond, for example, to particular predetermined arrangements of one or more logic gates, flip-flops, latches, etc. In order to determine if the overall circuit meets timing requirements, it is important to have accurate models of signal propagation delay through each of the cells. Other types of cell information, including, for example, output voltage slew, timing constraints such as setup and hold times, power consumption, and capacitive load, can also be modeled. Such models also help the designer optimize circuit performance while avoiding metastable conditions.
In an example of typical conventional practice, the cell propagation delay is modeled as a function of at least two independent variables, such as input voltage slew and output capacitive load. In one approach of this type, delay measurements are obtained, using circuit simulation software such as SPICE, for different values of input voltage slew and output capacitive load. The measured data points are stored in a two-dimensional (2D) table indexed by the particular input voltage slew and output capacitive load values used to obtain those data points. In order to determine the cell delay at other input voltage slew or output capacitive load values, linear interpolation between the measured data points is used.
Another example of conventional practice involves storing SPICE extracted output current or voltage waveforms, rather than explicit delay and output slew values. These waveforms, also arrayed in input slew and output load dependent tables, are taken directly into an analysis tool. The analysis tool then calculates more accurate delays and output slews using sophisticated interpolation and integration techniques.
It is also known to fit the delay measurement data to a multi-variable polynomial model. The polynomial model can then be evaluated at any input voltage slew and output capacitive load values in order to obtain the corresponding delay. Examples of polynomial modeling techniques of this type are disclosed in F. Wang et al., “Scalable Polynomial Delay Model for Logic and Physical Synthesis,” Synopsys Inc., 2000, and U.S. Pat. No. 6,272,664, entitled “System and Method for Using Scalable Polynomials to Translate a Look-Up Table Delay Model into a Memory Efficient Model,” both incorporated by reference herein. Polynomial models can also be configured to incorporate additional independent variables, such as supply voltage and temperature.
U.S. patent application Ser. No. 11/187,455, filed Jul. 22, 2005 and entitled “Multi-Variable Polynomial Modeling Techniques for Use in Integrated Circuit Design,” which is commonly assigned herewith and incorporated by reference herein, discloses an improved polynomial modeling technique that provides a higher level of accuracy than the above-noted conventional techniques, without significantly increasing the complexity of the modeling process and its associated computation and storage requirements.
Despite the advances provided by the modeling techniques disclosed in the above-cited patent application, a need remains for further improvements. For example, certain basic assumptions of typical cell modeling techniques, particularly with regard to upstream driver strength, can limit the accuracy of the resulting models. This issue is of primary concern for certain types of circuit elements, such as transmission gates or pass gates. The modeling deficiencies relating to such elements may result in the corresponding integrated circuit failing to operate as intended.